📕 subnode [[@KGBicheno/tpu_chip]]
in 📚 node [[tpu_chip]]
📓
garden/KGBicheno/Artificial Intelligence/Introduction to AI/Week 3 - Introduction/Definitions/Tpu_Chip.md by @KGBicheno
TPU chip
Go back to the [[AI Glossary]]
A programmable linear algebra accelerator with on-chip high bandwidth memory that is optimized for machine learning workloads. Multiple TPU chips are deployed on a TPU device.
📖 stoas
- public document at doc.anagora.org/tpu_chip
- video call at meet.jit.si/tpu_chip